Abstract
The self-heating effect on Si1-xGex based FinFETs is analyzed and investigated with different device structures/dimensions, Ge concentration, and operated voltages. The module-level material properties of the thermal conductivities (k) in Si and Ge with different operated temperature (T), material thickness (t), and impurity concentration (N) are calibrated by the experimental thermo-electric measurement firstly in our simulation model. The maximum chip temperature in the Ge FinFETs is found to be ∼50 °C higher than in the Si FinFETs due to the poor intrinsic material property of k in Ge material. This seriously limits the development of the Ge FinFETs in the future scaled logic devices even Si1-xGex material (x>0.8) has the higher intrinsic carrier mobility than pure Si. One of the possible solutions to avoid this self-heating effect in Si1-xGex based FinFETs is to reduce the operated voltage (<0.8V) to get the optimal device operated window among different boundary conditions including the acceptable chip temperature and the higher carrier mobility in the device.
Highlights
As we known, Self-Heating Effect (SHE) in the Complementary Metal-Oxide-Semiconductor (CMOS) logic transistors is becoming increasingly important when the dimension of the device is continuously scaled down
In order to calibrate our developed finite element simulation model for improving the accuracy of simulation, the k values in Si and Ge are extracted aM.-H
A well calibrated three-dimension (3D) device simulation deck is used in this work where the source/drain and channel doping profiles of realized devices were extracted from Monte Carlo implant simulations
Summary
Self-Heating Effect (SHE) in the Complementary Metal-Oxide-Semiconductor (CMOS) logic transistors is becoming increasingly important when the dimension of the device is continuously scaled down. The investigation of self-heating effect on Si1-xGex FinFETs with different device structures, Ge concentration, and operated voltages
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