The integration of alternative contact cleaning techniques for future DRAM technology nodes

Abstract

Conventional DRAM contact to Si cleaning methods are using wet HF-based chemistry to remove the native SiO 2 from the contact bottom and reduce the contact resistance [M.R. Baklanov, et al., J. Electrochem. Soc. 145 (9) (1998) 3240–3246]. With further scaling of the contact dimensions the distance between the contacts to the bitline (CB) and the adjacent gate conductors (GC) is decreasing. This is leading to increased parasitic capacitance between the CB and the GC and increased total bitline capacitance. The high bitline capacitance results in large signal delays, poor transfer ratio and thus bad signal margin and worse retention. In addition it is a general limitation for the number of cells attached to this bitline. For future DRAMs the need for small chip size is driving the reduction of the bitline capacitance and keeping the distance between the CB and the GC becomes a critical challenge. Typically, the material separating the CB from the GC is LPCVD TEOS. Furthermore, the selectivity of the wet HF-based chemistry of the as-deposited LPCVD TEOS to thermal SiO 2 is in the order of 3:1. This is resulting in high removal amount of LPCVD TEOS for a given removal of native SiO 2.