The Influence of Interface Traps on the High Frequency and High Temperature Performance of SiC Field Effect Transistors

Abstract

ABSTRACTFast and slow interface traps can considerably deteriorate the performance of field effect transistors. Slow interface traps, by slowly changing their charge occupancy, contribute to a drift in the quiescent operation point of the transistor, while fast traps deteriorate the device performance by contributing to both amplitude and phase current noise. They also result in a non-equilibrium surface depletion layer between gate and source which increases the gate-to-source parasitic resistance and deteriorates the device transconductance. We examine these different effects and present some preliminary data regarding interface traps in boron-doped 611-SiC.