The implementation of the attributed recursive descent architecture in VAX-11/780 microcode

Abstract

This paper describes a case study in the implementation of a special purpose architecture on a particular microprogrammable engine. The host engine used is the VAX-11/780; the target architecture is one tailored for implementing recursive descent translators. The paper describes the mapping of the target resources onto the host machine including a discussion of the issues involved in interfacing with the normal VAX environment. The architecture specification does not mandate the exact bit-level representation of the target architecture instructions allowing a more efficient emulator to be constructed. Many of the important design decisions involve choosing instruction representations to effectively utilize the host engine. The paper concludes with discussion of the considerable shortcomings of this approach, of the suitability of the VAX-11/780 as an underlying engine for the target architecture, and of the implications of the study for universal host machines.