Abstract
This paper presents a new observation in sub-60nm multi-finger (MF) nMOSFETs with nearly the same dc characteristics like channel current (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf> ) and transconductance (g <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</inf> ) from different dies/lots but a dramatic difference at high frequency parameters, such as intrinsic gate capacitances (C <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gg</inf> ) and unit gain cut-off frequency f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> after a clean deembedding to the bottom metal. The experimental results reveal an important finding that nanoscale devices even with inter-dies/lots process variations may keep the golden die target for dc and logic circuits performance but exhibit a significant deviation in high frequency performance. A comprehensive high frequency characterization and precise device parameters extraction has been carried out on various MF nMOSFETs to identify the root causes and explore the underlying mechanisms.
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