The High-Performance Design of a General Spiking Convolution Computation Unit for Supporting Neuromorphic Hardware Acceleration

Abstract

Recently, the design of spiking neural networks (SNNs) processors based on FPGA have become a hot research topic for their low power and high efficiency. However, most existing works lack flexibility in configuration to accomplish efficient computation of deep SNNs with different network structures (e.g., residuals). In this brief, a high-performance general spiking convolution processing unit and the corresponding hardware architecture (named SCPU) is designed to support both standard and residual convolution; then, a neuromorphic processor containing SCPU (called FPGA-SCPP) is implemented on Xilinx Virtex-7 FPGA. Specifically, the model parameters are fused and quantified to reduce the computational amounts and simplify its hardware implementation. And a spike event processing unit is designed based on event computation and direct data flow to complete the standard and residual convolution computations. The experimental results show the FPGA-SCPP can effectively deploy different large-scale SNNs models such as VGG and ResNet, with the highest recognition accuracies of 92.45% and 68.55% on CIFAR-10/CIFAR-100, respectively. Our FPGA-SCPP has a computational power of only 1.7W and a frame rate of 40fps, which improves inference speed by about 6 times and reduces power consumption by 3 times compared to existing processors. Therefore, FPGA-SCPP can effectively accomplish the acceleration of deep SNNs, especially for models with spiking residual blocks.