Abstract

Wafer bonding technology promotes 3D system integration and packaing. In this paper, the Cu/Sn low-temperature bonding for 3D glass wafer stacking is studied. The effects of temperature, pressure and time on the bonding process are demonstrated by experiments and simulations. The formation of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">${\text{Cu}_{3}\text{Sn}}$</tex> is incorporated into Cu/Sn bonding interface. For 5G devices, such as the applications of millimeter wave, terahertz and internet of things (IoT), advanced packaging using glass substrate with excellent electrical properties is promising. Based on the laser inducing and wet etching, through glass vias (TGV) were fabricated, and the vias wre filled with Cu. Then, the Cu/Sn RDL is electroplated to form a stacked structure for multi-layer bonding. To optimize the process, Cu/Sn bonding surface and TGV cross section are analyzed by scanning electron microscope (SEM). And the ratio of Cu/Sn alloy are measured with an energy spectrometer. Based on X-ray photography, there are no bonding defects. The seal ring formed by bonding can effectively protect the electrical signals transmitted in the TGV. There is no leakage in the seal ring, the amount of Sn overflow during the bonding process is limited, and it does not affect the TGV and metal trace near the sealing ring.

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