Integrated process for high aspect ratio through glass vias

Abstract

Increasing demands for bandwidth in high performance computing, Fifth-generation (5G) communication, and Internet of Things (IOT) applications have driven the migration to 2.5D and 3D interposers, requiring less high frequency loss and higher ratio of hole depth/dimension for vertical interconnections. Through silicon via (TSV) has been utilized to minimize the distance between chips by vertically stacking chips in 3D-IC in some high-end products. It has been proved that a high data transmission, a wider bandwidth, a smaller footprint, and lower power consumption can be achieved. Meantime, TSV technologies possess many challenges such as high fabrication complexity and its unacceptable cost. Glass is an ideal interposer material due to its insulating property, large panel availability and coefficient of thermal expansion (CTE) match to silicon. Through glass vias (TGVs) fabrication is the key module to TGV interposer process integration. In this paper, processes, including TGVs etch, seed layer and Copper plating have been presented in detail. Through careful consideration and optimization of the above mentioned aspects, TGVs with 30um wide, 150um deep have been successfully fabricated. For TGVs fabrication, photosensitive glass was used to create the vias' area, and then wet etching was processed to get blind vias about 30um hole dimension and 150um depth. After high aspect ratio sputtering of Ti/Cu, copper full-filling was tested and no void was verified by X-ray image. For testing the integration ability of glass interposer, some inductors was fabricated on the glass wafer and its performance after the total processes was tested which Q factor was bigger than 45.