The Finite Element Analysis of Weak Spots in Interconnects and Packages

Abstract

Concerning the mechanical stress and the electrical-mechanical behavior ULSI multilevel metallization systems are more and more sensitive against influences of geometrical and material changes. The mechanical and electrical reliability of these metallization systems is influenced by this. The reliability of such metallization systems is investigated by thermal and thermal-electrical accelerated stress tests under high temperature load. This leads to degradation due to electro-, thermoand stress migration. This is one major concern in reliability investigations. Generally measurements are time consuming, expensive and the time-to-market cycle is in the focus of interest too. The prediction of local weak spots in interconnects, vias and solder bumps by finite element simulations are a helpful procedure. Beside this the modern 3-d integration leads to more complex material compositions in the systems concerning the coefficient of thermal expansion (CTE) and other material properties. Higher applied currents on the interconnects and bumps result in Joule heating, high temperature gradients and mechanical stress gradients in the bump and metallization systems. The temperature gradients are much higher compared to systems with wide interconnect lines and bumps with large diameters like in conventional packages. Due to this in ball grid array (BGA) bumps as well as μ-bumps and small through silicon via (TSV) connections current induced migration effects as electromigration (EM) and as result of the high temperature gradients thermomigration (TM) can occur. In interconnects consisting of copper caused by stress gradients due to the different material properties under high temperature load also stress migration (SM) occurs.