The energy release rate of the micro-cracks in a ultralow-k chip during the flip chip process

Abstract

The ultralow-k (ULK) dielectric materials are used in 40nm chip technologies to reduce RC delays and improve chip performances. The ULK materials have much higher porosity and become fragile in the mechanics. Fractures may take place due to the themal stress in typical packaging process, e.g. the flip chip reflow process. To evaluate the stresses and fracture behaviors in the ultralow-k chips, we carried out a finite element analysis by sub-modeling method. In the model an effective thin layer that included the microstructures on the surface of the ultralow-k chip was introduced in the global model and the one-level sub-model was adopted to perform the stress and fracture analysis during the flip-chip process. The micro-cracks in the ultralow-k layers were introduced in the sub-model. The energy release rate (ERR) at the tip of the micro-crack that is at varied locations was compared. The results indicate that the crack of ULK material transmits from the outer layers to the inner layers when the first principal stress is increased. The cracks in the seventh to ninth layers are most likely to propagate in a flip chip reflow process.