A study on the chip-package-interaction for advanced devices with ultra low-k dielectric

Abstract

The continuous scaling down of devices has led to increase use of smaller interconnect features that can increase the interconnection delays. In order to reduce such interconnection delays, low-k dielectric has been introduced, and then for advanced devices that require further reduction in delays, porous structure called ultra low-k (ULK) material has been developed. The porous structure of ULK dielectric has poor elastic stiffness and fracture resistance that is vulnerable to catastrophic failures such as ULK cracks or delamination during packaging processes or reliability tests. A flip chip test vehicle has been designed and prepared to experimentally characterize the ULK related failures such as white bumps, which are localized ULK cracks found underneath the flip chip bumps. Stresses acting on ULK layer have been analyzed using finite element methods with global and local modeling. Test results show packaging material set with low coefficient of thermal expansion (CTE) substrate and high glasstransition temperature underfill improved the structural integrity of chip-package assembly by reducing the stresses on ULK layer caused by CTE mismatch between chip and package substrate. Cu pillar bumps are more susceptible to white bump failure, and large bump size can reduce the stress on the ULK layer. Package structure with thinner chip has shown to be effective in reducing white bump failures. Besides the package material and geometry, structure and material of the back-end-of-line (BEOL) layer has also shown to be critical. White bump failures were concentrated underneath the pattern where some vias were missing. In view of ULK interface, etch stop layer material showed influence on white bump failure ratio. Proper selection of package materials and structure as well as carefully placed metal, via density and ESL material are critical in achieving structurally stable chip-package-interaction.