Abstract
Hysteresis in the threshold voltage of MOSFETs due to oxide traps is discussed, which can impose serious limitations on the accuracy and speed of analog circuits. The measured magnitude of the input-referred hysteresis ranges from 100 mu V to more than 1 mV in NMOS devices stressed with positive gate-source voltages ranging from 1 to 5 V on microsecond-to-millisecond time scales. This hysteresis is explained by a model in which electrons tunnel to oxide traps close to the interface.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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