The effects of channel width tapering on the power dissipation of serially connected MOSFETs

Abstract

Transistor channel width tapering in serial MOSFET chains is shown to decrease the propagation delay, power dissipation, and physical area of VLSI circuits. Tapering is the process of decreasing the size of each MOSFET transistor width along a serial chain such that the largest transistor is connected to the power supply and the smallest is connected to the output node. It is demonstrated that, in many cases, tapering decreases delay and changes the shape of the output waveform such that the time during which a load inverter is conducting short-circuit current is reduced. This decrease in short-circuit current also occurs in many cases where tapering does not offer a speed advantage. Dynamic CV/sup 2/f power dissipation of the serial chain is reduced. This behavior permits a designer to trade-off speed for a reduction in short-circuit and dynamic power dissipation, a trade-off not normally available with untapered chains. >