The Effect of Multiple Interface States and nc-Si Dots in a Nc-Si Floating Gate MOS Structure Measured by their G—V Characteristics

Abstract

An nc-Si floating gate MOS structure is fabricated by thermal annealing of SiNx/a-Si/SiO2. There are nc-Si dots isolated by a-Si due to partial crystallization. Conductance-voltage (G—V) measurements are performed to investigate the effect of multiple interface states including Si-sub/SiO2, a-Si related (as-deposited sample) and nc-Si (annealed sample) in a charge trapping/releasing process. Double conductance peaks located in the depletion and weak inversion regions are found in our study. For the as-deposited sample, the Si-sub/SiO2 related G—V peak with weak intensity shifts to the negative as test frequency increases. The a-Si related G—V peak with strong intensity shifts slightly with the increasing frequency. For the annealed sample, little change appears in the intensity and shift of Si-sub/SiO2 related G—V peaks. The position of a-Si/nc-Si related peak is independent of frequency, and its intensity is weaker compared to that of the as-deposited sample. It is also found that as the size of nc-Si becomes larger, the a-Si/nc-Si related peak shifts to the depletion region due to the size effect of nc-Si.