The Effect of Interfacial Layers on High-Performance Gate Dielectrics Processed by RTP-ALD

Abstract

In this paper we present the role of the ultrathin interfacial silicon-oxide layer on the performance of high-k dielectrics. We deposited by rapid thermal process atomic layer deposition (RTP-ALD) and studied the electrical conduction mechanism of the films. As the quality of the interfacial layer may seriously influence the performance of a high-dielectric-constant gate material, we designed a number of experiments to understand the role of the interfacial layer. Some of these experiments include the study of an identical thermal cycle with and without use of the precursor for the deposition of films. In the transmission electron microscopy (TEM) micrographs (especially in STEM-Z) the formation of amorphous silica and crystalline zirconia exhibit a distinct periodicity characteristic of spinodal decomposition. This feature, along with atomic-level sharpness of the interface, may hold the key to excellent electrical properties reported in this paper. The ultrathin interfacial silicon oxide layer has the ability to accommodate the strain between silicon and the mixed phase material without creating significant defects at the interface. © 2004 The Electrochemical Society. All rights reserved.