The Effect of Feedback Sampling Clock Jitter on the Performance of Direct Learning Digital Predistortion in Wideband Systems

Abstract

The sampling clock accuracy of the digital predistortion (DPD) feedback path is limited by nonideal electronic components, which introduces random clock jitter and thus degrades the system performance. In this letter, we analyzed the effect of feedback sampling clock jitter on the power amplifier (PA) model identification and hence on the DPD performance. The expression of the normalized mean square error (NMSE) caused by clock jitter is derived in terms of the variance of the jitter and the signal bandwidth. The theoretical analysis reveals that the performance degradation caused by clock jitter increases with the bandwidth of the orthogonal frequency division multiplex (OFDM) signal. Simulation results demonstrate that the NMSE performance degradation is consistent with the theoretical curve. The adjacent channel leakage ratio (ACLR) performance degradation for a long term evolution (LTE)-advanced signal with 100 MHz bandwidth and a clock jitter of 0.5 ps is about 5 dB greater than the performance degradation caused by conventional feedback impairment model.