The effect of CESL and dummy poly gate for n-type MOSFETs with short Si0.75Ge0.25 channel

Abstract

In this investigation, the n-channel metal–oxide–semiconductor file–effect transistor (MOSFET) with contact–etch–stop–layer (CESL) stressor, SiGe channel, and dummy poly gate is proposed. The simulated technique is utilized to explore the stress distribution of nMOSFET with the channel region induced by foregoing mechanical. We use ANSYS software, which is based on finite element analysis (FEA), to simulate the stress distribution in the channel region. The simulation results indicated the CESL and SiGe channel significantly affected the stress distribution within the channel region. The sources of loading are 1.1, 2, and 3 GPa tensile CESL (t-CESL) and a SiGe channel structure with 25% germanium (Ge) mole fraction. The effect of dummy poly gate is discussed, including the dummy poly gate number and various pitches of the dummy poly gate. The simulation results indicate that the pitch of the dummy poly gate substantially influences the number of dummy poly gates. The electron mobility enhancement in the inversion layer of n-channel MOSFET was discussed. Electron mobility enhancement was evaluated by piezoresistance coefficients. Hence, the percentages of improvement of electron mobility with different structural conditions were compared. The relationships between stress distribution in the channel and dummy poly gate layout could be understood clearly through systematic analysis.