The development of a fully implanted 3 micron poly-gate NMOS technology — (Part 1)

Abstract

Initial efforts have been made to develop a fully implanted 3 micron poly-gate NMOS technology for fabricating an 8-bit binary counter chip. The MOS transistors in the circuit, initially designed for 8 micron gate length were scaled down to 3 micron by over-exposure and over-etching techniques. The process consists of a double boron ion implantation. A shallow boron implant was used to raise the threshold voltage, and a second, deeper boron implant was used to increase the punch-through voltage between the source and drain. The process is especially beneficial for maintaining low junction capacitance and low threshold substrate sensitivity of the high resistivity substrates in the case of short channel devices and for high speed logic circuit applications. Results of measurements on MOS transistor test structures are presented in the paper.