The design of reliable controller for interprocessor communication network using ATM switch

Abstract

This paper describes the design of reliable controller for interprocessor communication network (IPCN), which sends and receives information among processors through asynchronous transfer mode (ATM) switches. Hardware mainly is composed of a transmitting section, in which messages are decomposed into cells, and a receiving section, in which cells are assembled into messages. Software is composed of an interface section for communicating with an application program and a driver section for driving IPC control device. The IPC controller is doubly designed, so it is possible to provides continuous service for the system when upgrading or changing the software. ATM adaptation layer (AAL) type 5 is used for the format of IPC messages. IPC header information as well as additional information for routing of ATM cells are also used. This paper also presents characteristics and requirements for IPC through ATM switch, and computes message error rate and message retransmission rate with varying user message size. Finally, this paper derives the equation of the optimal message length considering retransmission.