The Design of Compact SM4 Encryption and Decryption Circuits That Are Resistant to Bypass Attack

Fang Zhou,Xiangli Bu,Benjun Zhang,Ning Wu

doi:10.3390/electronics9071102

Fang Zhou, Xiangli Bu + Show 2 more

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https://doi.org/10.3390/electronics9071102

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Abstract

In order to achieve the purpose of defending against side channel attacks, a compact SM4 circuit was designed based on the mask and random delay technique, and the linear transformation module was designed with random insertion of the pseudo operation method. By analyzing the glitch data generated by the S-box of SM4 with different inputs, the security against glitch attacks was confirmed. Then, the DPA (Differential Power Analysis) was performed on the designed circuit. The key could not be successfully obtained even in the case of 100,000 power curves, so that the safety of SM4 against DPA is verified. Finally, using Synopsys DC (Design Compiler, Mountain View, CA94043DC, USA) to synthesize the designed circuit, the results show that the area of the designed circuit in the SMIC 0.18 process is 82,734 μm2, which is 48% smaller than results reported in other papers.

Highlights

The SM4 algorithm is a block symmetric cipher algorithm announced by Chinese National CipherManagement Committee Office in January 2006 and it has been widely used in various fields of information security in China, such as wireless local area network (WLAN), WLAN Authentication and Privacy Infrastructure (WAPI), storage device and the smart card system
Because the composite field mask S-box is easy attacked by glitch attacks, this paper further proposes the random delay method to change the time delay of the input data of the composite field mask S-box
This paper focuses on the compact implementation of SM4 encryption and decryption circuits that are resistant to bypass attacks

Summary

Introduction

The SM4 algorithm is a block symmetric cipher algorithm announced by Chinese National CipherManagement Committee Office in January 2006 and it has been widely used in various fields of information security in China, such as wireless local area network (WLAN), WLAN Authentication and Privacy Infrastructure (WAPI), storage device and the smart card system. As the SM4 algorithm is mostly used in high-speed and resource constrained applications, it is very necessary to design and implement the compact circuit of SM4. DPA is a typical SCA (side channel attack) method which performs a correlation analysis by collecting the power consumption of the operation. According to the correlation between sensitive information in the operation and the instantaneous power consumption of the CMOS circuit, DPA can quickly recover the key of SM4. It has the advantages of simple implementation, high efficiency, and short attack time. The goal of this work is to study compact SM4 circuits resistant to SCA for resource constrained applications

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