A Novel Sizing Method Aiming Security Against Differential Power Analysis

Abstract

The confidential information provided by embedded cryptosystems are threatened by Side Channel Attacks (SCA). Differential Power Analysis (DPA) is an SCA that correlates the dependency between processed data and the system's power consumption in order to obtain the secret information. Circuit-level countermeasures against DPA aim at achieving the data-independent supply current. This work proposes a sizing methodology focused on equalizing the power dissipation of logic gates towards increasing security against DPA attacks. The developed algorithm searches for an optimal sizing by iteratively expanding the solution scope and verifying its consistency through SPICE simulations. Topologies used as countermeasures to DPA attacks were submitted to the proposed methodology and their security metrics were evaluated. Results from DPA attacks show that circuits sized with the proposed method had their keys less likely to be broken for all selection functions and key searches tested.