The Design of an Ultra-Low-Voltage Ultra-Low-Power 7.5 GHz LNA in 0.13µm CMOS Technology

Abstract

In this paper a low noise amplifier (LNA) is designed at 7.5 GHz with ultra-low power consumption in 0.13µm CMOS technology. New and precise calculations for input and output impedance are calculated and compared with other works. The forward body biasing technique is utilized to bring down power consumption of the circuit. MATLAB, HSPICE, Advanced Design System (ADS), and TSMC 0.13 µm CMOS process are used to simulate the LNA. The performance of the circuit is scrutinized with and without spiral inductors. With lumped inductors, 0.42 dB, -27dB, -4dB, 20dB, 156µW, and -3 are achieved for noise figure (NF), input impedance matching (S11), output impedance matching (S22), power gain (S21), power consumption, and the third order intercept point (IIP3) respectively. Plus, with spiral inductors 2.3dB, -23dB, -5dB, 10dB, 156µW, and -7 are achieved for noise figure (NF), input impedance matching (S11), output impedance matching (S22), power gain (S21), power consumption, and the third order intercept point (IIP3) respectively.