The Design and Fabrication of 0.35 µm Single-Polysilicon Self-Aligned Bipolar Transistors

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Two innovative process technologies are introduced to overcome problems related to the downscaling of single-polysilicon self-aligned bipolar transistors. First, the use of a selective silicon deposition step before Ti salicidation of the structure is shown to improve TiSi2 formation on narrow As-doped polysilicon emitters. At the same time, the elevation of the extrinsic base regions around the emitter causes a significant reduction of peripheral electron recombination effects. Second, the implantation of the intrinsic base at a large tilt angle (LATIB) is demonstrated to suppress emitter-to-collector punchthrough along the isolation edges. The first 0.35 µm single-polysilicon self-aligned bipolar transistors fabricated using a 200 mm complementary metal oxide semiconductor (CMOS) derived bipolar process integrating these novel process technologies are described.