Abstract
Summary form only given, as follows. The authors show that high-connectivity neural networks are difficult to realize with VLSI chips. Neural networks are modeled by the composition or a family for bipartite graphs that reflect the connectivity found in applications. The number of crossings when they are embedded in the plane (their crossing number) provides a lower bound on the area needed to realize them in VLSI. The authors develop lower bounds to the crossing number of neural network graphs under a few simple assumptions about the way edges are embedded in the plane. A graph that is the subgraph of many neural network graphs is the complete bipartite graph. The authors show that this graph has a crossing number that is at least cubic in the number of input and output vertices. >
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