The constraints of vias and layers and their impact on PCB design strategy

Abstract

This paper explores the use of models of substrate behaviour to examine the wireability constraints on PCBs due to signal layers and buried and through vias. The importance of product scale as a factor affecting technology choice is examined in detail, and the factors that decide the need for multi‐layer construction and buried and through vias are discussed. Large PCB layouts are constrained by lack of space for traces ‐ trace bound; a limitation that can be removed by using multi‐layers and through hole vias. Small PCB layouts are constrained by lack of space for vias ‐ via bound; buried vias and landless vias are particularly useful for maximising wiring density under these conditions. A further observation is that the use of multiple layers offers diminishing returns as each further layer is added. For small high wiring density PCBs approximately four layers supporting blind vias can give excellent support for the use of high I/O (Input/Output) density packages.