Abstract

The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit bricks in integrated circuits (ICs) have constantly changed during the past five decades. The driving force for such scientific and technological development is to reduce the production price, power consumption and faster carrier transport in the transistor channel. Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved. This article highlights the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and then presents how the process flow faces different technological challenges. The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future FinFETs.

Highlights

  • Being followed by Moore’s law, the demands from micro-electronics industry drives more and more powerful transistors with higher integrating density and lower power consumption in integrated circuits (ICs)

  • To minimize short channel effects (SCEs), device substrates were changed from bulk silicon to silicon on insulator (SOI) [2], but the device structures transformed from two dimensional (2D) planar ones to three dimensional (3D) devices

  • To further enhance the channel mobility in planar MOSFETs, the Ge content in SiGe S/D has been continuously increased from 17% to 40% in 90 nm to 22 nm node, respectively [36,37,38,39,40]

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Summary

Introduction

Being followed by Moore’s law, the demands from micro-electronics industry drives more and more powerful transistors with higher integrating density and lower power consumption in integrated circuits (ICs) Because of such a high scaling, local electrical fields increase and many side effects, e.g., short channel effects (SCEs) are created [1]. To minimize SCEs, device substrates were changed from bulk silicon to silicon on insulator (SOI) [2], but the device structures transformed from two dimensional (2D) planar ones to three dimensional (3D) devices Through, this technological evolution transistors e.g., fin field effective transistor (FinFET), gate all around devices and nanowire or nanosheet were manufactured because of their excellent short-channel control [3,4,5,6,7]. The discussions have a focus on 2D to 3D transition in FETs

Lithography of Nano-Scaled Transistors
Overlay
Challenges in EUV Lithography
Process Integration of New Transistor Architecture
Precise
Precise and Uniform Fin Formation
Uniform Junction Formation in Fin
Stress Engineering
Schematic
Stress Measurements in Nano-Scaled Transistors
Evolution of HKMG
Atomic Layer Deposition of Metal Gate
Additional Sources of Variation
Common Challenges
Dopant Implantation in CMOS
Challenge of Ion Implantation in 3D Structure Devices
Conformal Doping
Damage Control
Depth Loading Control of Fin Etching
Gate Etching Control
16. Cross-section
STI Process for the Gate
Gate Process
20. Vertically
Challenges in Processing
22. Theproblems lowest defect
Design
Findings
Conclusions

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