The application of statistical simulation to automated analog test development

Abstract

The CAPITOL circuit simulation program provides algorithms for selecting tests and formulating test limits for linear and nonlinear analog circuits subject to random deviations from nominal component values. These analog test development algorithms are implemented as part of the Monte Carlo statistical simulation capability of the program. The algorithms are based on fundamental principles of statistics such as Bayes' theorem. They operate independently from the function performed by the circuit, its fabrication technology, and the nature of the component statistics. Consequently these algorithms; have had application to a wide range of problems in analog circuit testing and fault diagnosis. This paper describes the algorithms and presents examples of their use. The examples highlight applications in predicting and diagnosing failure modes due to random variation of component values.