The application of pattern correlation method between maps of failure bins and electrical parameters in fault isolation

Abstract

Normally, it is difficult to isolate and identify the root cause for sort failures, especially for functional failures. This problem is worst for the wafer foundry because of the limited information on the product from customer. Sort test failures are generally analysed by either a correlation study between yield and electrical test (ET) data on the ET structure in a scribe line or a fault isolation technique. The yield correlation method is not as efficient because of the complicated sort test, the limited electrical data (usually only a few sites for production wafers), and the variation of yield patterns and ET behaviour among wafers and lots. The fault isolation techniques may not be able to capture the failure defect, especially for functional failures. One of the major limitations for yield analysis is the irregular yield pattern and its variation among wafers and lots. An irregular yield pattern means a correspondingly similar irregular ET data pattern for those failure-related parameters. In other words, those failure-related ET parameters should have higher correlation with the yield map than the rest of parameters. Thus, based on the quantitative calculation of the correlation between the maps of failure bins and the ET parameters, those ET parameters with high correlation can be identified and reasonably believed to be failure-related. In this paper, the pattern correlation method is introduced and applied for a true case of functional failure with via issue.