The Amorphous-Si CMP process improvement for L14 nm FinFET technology node

Abstract

Multiple gate field-effect transistors (MuGFET) are generally used in modern time semiconductor field due to better transistor current flow. However in the last advanced generation, MuGFET has transferred to Fin Field Effect Transistor (FinFET) structure with 3 dimensional (3-D) geometry to enable the minimize off-state leakage currents, high transistor current flow and quick switch…etc. advantages. But 3D structure will limit the depth of focus (DOF) of lithography. Chemical Mechanical polishing (CMP) planarization process has become more and more important to improve this issue in FinFET production. At L14 node CMP processes, a new Amorphous Si (A-Si) CMP process is introduced to reduce the roughness after the Amorphous Silicon deposition of gate. In this study, a robust ASICMP process with better A-Si polishing profile (range control), lower defectivity and better thickness control has been evaluated to meet the ASICMP process criteria at 14nm node. Optimizing the process control algorithm and down force condition for each polishing zone could improve process stable and range control. Fine tune full-vision spectrum can obvious enhance thickness control accurately.