Abstract
As technology scaling progresses into 65nm node and below, On Chip Variation (OCV) specifically thickness variation due to Chemical Mechanical Polishing (CMP) processes becomes relatively larger, as such it needs to be taken into consideration into post layout RC extraction and timing flow. Traditionally manufacturing effects due to lithography and CMP processes are captured using rule based look up tables which are generally included in the technology files of the RC extraction tools. However, due to complex nature of the CMP process and its design dependency, the generic rules can not capture thickness variation for various design topology accurately. Therefore CMP models are used to simulate design specific thickness variation profile, based on the calibrated manufacturing process. In this paper, we demonstrate that by incorporating CMP model in the post layout RC extraction flow, the thickness variations are reflected more accurately. Therefore, the capacitance values extracted are different from those obtained using rule based approach. As a result, new timing violations are detected using model based approach.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
