The 128-bit AES design by using FPGA

Abstract

Advanced Encryption Standard (AES) is a common symmetric encryption algorithm and widely implemented in Wireless Local Area Network (WLAN) and Bluetooth controller for security services in its application. This paper presents a 128-bit data path with 128-bit, 192-bit or 256-bit key size. The purpose of the design is high throughput and low area design of AES. The AES methodology is by using Field-Programmable Gate Array (FPGA) and Xilinx Virtex-7 XC7VX485T as a tool to obtain simulation results through Verilog Hardware Description Language (HDL). This design utilized a 2730 Slices with the throughput of 12.9 Gbps. The design is suitable for the portable device application which requires data security with a high throughput and speed.