Abstract
It is known that the ISCAS85 circuit c6288 contains an exponential number of paths and more than 99% of the path delay faults are untestable. Most ATPG tools, which can efficiently handle other circuits, fail on c6288. The logic structure ofc6288 is studied and the main features, which cause false paths, are revealed. A heuristic, which significantly helps the path delay fault test generation for this circuit, is presented. Experimental results show that our methodology is able to efficiently generate testable paths for c6288.
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