Testing ripple carry adder using bist architecture

Abstract

Very Large-Scale Integration has a greater impact on the developing circuit technology. The Cost and Size has been gradually reducing since years but increased the circuit complexity, there are problems which may affect the growth of VLSI technology. Among them one of major problem is circuit testing. To resolve this issue, we implement Built in Self-Test (BIST). BIST architecture is used to test the circuit itself. Engineers Design BIST to achieve high reliability and low repair cycle times. We implement Linear Feedback Shift Registers (LFSR) to generate the pseudo random test pattern and implement a ripple carry adder as circuit under test and Multiple Input Signature Register(MISR) as output response analyzer and test patterns are given to circuit under test and outputs are obtained these are compared with the actual outputs to test whether the circuit is faulty or not. To check whether the circuit is faulty or fault free we check the obtained outputs with actual outputs using Signature Analysis.