Abstract
This paper presents a combined approach for testing logic and routing resources in programmable logic devices (PLDs). The proposed approach is based on configuring the PLD using different arrangements such as built-in self-test schemes (for example, a parity chain) and one-dimensional arrays (with and without common inputs). It is proved that the proposed approach achieves 100% fault coverage under a fault model consisting of a single fault in the logic resources and active routing devices, or multiple faults in the interconnection channels and input/output lines.
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