State transition graph analysis as a key to BIST fault coverage

Abstract

The authors consider the analysis of the state transition graph (STG) as a key to understanding the state and fault coverage of BIST (built-in self-test) schemes. Some interesting topological properties of STGs are found. These may be exploited when BIST schemes are being designed. Specifically, the problem of limit cycles in STGs is discussed, and ways of defining initial states to yield long paths before state repetition are presented. One BIST scheme that has modest overhead requirements and is based on serial shift registers is given. The scheme is applied to some of the ISCAS-89 benchmark circuits, and experimental results on fault coverage are presented. >