Abstract
In high-energy physics experiments, it is a trend to implement digitalization in the front end of readout electronics based on Application Specific Integrated Circuits (ASICs), which are exposed to the radiation environment. As an important part of ASIC, SRAM (Static Random-Access Memory) is impressionable to Single Event Upset (SEU) due to the radiation environment. Therefore, a new SEU-tolerant SRAM cell structure was designed in our previous work. In this paper, a test system for evaluating the radiation tolerance effect of this SRAM structure is described, and the chip’s performance in the radiation environment is presented. The test results show that the new SRAM cell upset cross-section was reduced by five times compared with the ordinary 6T cell without increasing the power consumption.
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