Testable design with PLA macros

Abstract

The complexity of VLSI systems forces toward structured approaches to reduce both design time and test generation effort. PLA's and scan path have been widely reported to be efficient avenues of attack. In this paper an easily testable structure and related strategies are presented. Circuits are assumed to be based on the interconnection of combinatorial macros, mostly implemented by PLA's; tests are generated locally and then expressed in terms of primary inputs and outputs using a topological approach as general strategy and algebraic techniques for the propagation of signals through macros. Propagation is dealt with by new algorithms. As the problem of test generation is NP-hard, a set of heuristics is introduced to keep the amount of computation reasonable.