Test Scheduling for Network-on-Chip Using XY-Direction Connected Subgraph Partition and Multiple Test Clocks

Abstract

It is attractive to reuse the on-chip functional interconnects as test access mechanism (TAM) in network-on-chip (NoC) system testing. However, in the methodology of NoC-reuse as TAM, the influence factors in NoC testing significantly increased. To further reduce test time and show significant gains over other work, we propose XY-direction connected subgraph partition (XYCSP) approach to eliminate the path conflicts before testing, and concurrently determine the position of test access points. We then present a multiple test clock strategy to bridge the gap between the NoC channel bandwidth and the core test wrapper bandwidth. With the help of adaptive probability gate quantum-inspired evolutionary algorithm (APGQEA) strategy, which blends adaptive strategy and multi-nary oriented techniques, the proposed NoC test scheduling algorithm permits quick exploration and exploitation of the solution space. Moreover, power constraints are also taken into account. Experimental results for the ITC'02 benchmarks show that the proposed scheme can achieve shorter test time compared to prior works.