Testing WiNoC-enabled multicore chips with BIST for wireless interconnects

Abstract

Complex multicore Systems-on-Chips (SoCs) require large testing time and consume high amounts of power during post manufacturing test. With the advent of Network-on-Chip (NoC) based interconnections, the NoC has been envisioned to be reused as the Test Access Mechanism (TAM) to reduce hardware overheads for testing. Therefore, testing the TAM is critical as it provides the interconnection backbone for such chips and detecting a fault in the TAM can flag a faulty SoC early in the testing process. However, multi-hop data transfer over traditional NoCs can result in slow test times especially, for large multicore SoCs. In recent years, conventional NoC fabrics augmented with wireless transceivers to form Wireless NoCs (WiNoCs) have improved message latency and energy consumption in on-chip data transfer. Therefore, in this paper we propose to augment NoC-based TAMs with wireless interfaces to form a WiNoC based TAM (WiTAM) providing single-hop test delivery paths in the NoC. As the wireless transceivers themselves can be faulty, we propose a novel fault model and Built-In-Self-Test (BIST) based test methodology for the wireless interconnects. We present a model to estimate the test time and evaluate the testing time and power of the WiTAM. We demonstrate that the WiTAM can reduce the test time as well as the energy-delay product of testing of the WiNoC. Moreover, we show that test time for testing cores of a multicore SoC with WiTAM can also be reduced compared to a wired NoC.