Abstract
Test Pattern Generation for Transition Faults with Low Power using BS-LFSR and LOC
Highlights
IN Very Large Scale Integration (VLSI) technology one of the major problems is the power consumption, days Engineers are trying to reduce the power consumption in many ways [2]
Test patterns are generated through the Automatic Test Pattern Generation (ATPG) tool and it is applied to the Circuit Under Test (CUT) and finds the faults
In this paper we are going to compare the performance of 2 techniques Bit Swapping (BS)-Linear Feedback Shift Register (LFSR) and LOC for the transition faults
Summary
IN VLSI technology one of the major problems is the power consumption, days Engineers are trying to reduce the power consumption in many ways [2]. In VLSI one of the major problems is high power consumption; this is mainly due to the high switching transition because of the transition faults. In this paper targeting the transition faults with low power. In this paper we are going to compare the performance of 2 techniques BS-LFSR (bit swapping linear feedback shift register) and LOC (launch-off-capture) for the transition faults. Technique is LOC (Launch-off-capture) for transition fault testing; it has 3 cycles initialization cycle, launch cycle, capture cycle. By using these two techniques we are going to compare which one will achieve low power better than the other techniques by compare the area and delay
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