Abstract
A linear feedback shift register is commonly used as a test pattern generator in LBIST architectures. The test patterns are generated by TPG and are applied to the CUT. The patterns generated by TPG contribute to higher power dissipation in test mode as they lead to higher high switching activity within the CUT. In order to overcome this problem different TPGs are proposed by modifying the conventional LFSR. This paper presents comparative analysis of the seven different low power test pattern generators which are proposed in literature to achieve low power dissipation. An 8x8 multiplexer circuit is used as CUT. Of all the seven TPG’s compared modified clock scheme is the best suited TPG for the low test vector power aware architecture.
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