Test path generation and test scheduling for self-testable designs

Abstract

The high cost of chip testing makes testability an important aspect of any chip design. Early inclusion of test considerations into the design process can reduce test time and area overhead. We have developed an algorithm which defines built-in self-testing (BIST) tests for an RTL datapath. Datapath registers are chosen to be upgraded to testable registers to execute the define tests. Test time of an individual test is reduced by considering pattern randomness and error masking transparency properties of modules involved in the test. Parallelism between different tests is increased by reducing the number of conflicts between tests. Intertwining the creation of tests with the selection of testable registers in the datapath guides the choice of testable registers to a minimal area solution. The use of these metrics provides our system with an accurate estimate of test time, and therefore facilitates the definition of tests which reduce test application time. Experimental results show that our algorithm defines tests which require low test time. >