Test Generation for LSI: A Case Study

Abstract

A new automatic test generation approach for LSI circuits has been presented in the companion papers [1] [2]. In this paper we generate tests for a typical LSI circuit using the new approach. The goal of this study is to gain insight into the problems involved in using the test generation procedures. A formal model C for a 1-bit microprocessor slice is defined which has all the main features of commercially available bit slices such as the Am2901. The circuit C is modeled as a network of interconnected functional modules. The functions of the individual modules are described using binary decision diagrams, or equivalently using experiments derived from the diagrams. Using our test generation technique, we derive tests for the circuit C capable of detecting various faults covered by our fault model [1]. It is shown that backtracking is rarely needed while generating tests for C. Also, we show that generating a multiple vector test is not required for any of the faults considered in the study. The length of the circuit's test sequence is significantly reduced using the fault collapsing method. A discussion of how to model some of the features of LSI circuits that are not included in the circuit C is presented. A comparison between the length of the test generated by our method and other manually-generated ones is also presented.