Application of Tools Developed at the University of Iowa to ITC-99 Benchmarks

Abstract

We describe the application of the following tools to ITC-99 benchmark circuits. Deterministic test generation: The test generation procedure MIX [1], and its extension MIX + [2], combines several test generation approaches to derive test sequences exhibiting very high fault coverages at relatively low CPU times. It includes a simulation-based test generation procedure based on LOCSTEP [3], a deterministic test generation procedure, and a test generation procedure based on genetic optimization. It assumes fault detection under the restricted multiple observation time approach [4]. Property-based test generation: The test generation procedure PROPTEST [5], [6] uses several simulation-based techniques to generate test sequences without resorting to branch-and-bound procedures. The techniques include static compaction based on vector restoration [7] to capture the most effective test subsequences of the test sequence, holding of test vectors [8] and perturbation of test vectors. PROPTEST achieves very high fault coverages at very low test generation times in spite of its relatively low complexity. Identification of undetectable faults and removal of redundant faults: Identification of undetectable faults prior to test generation can save the potentially wasted effort in targeting undetectable faults. Redundant faults can be removed from the circuit as a way to simplify the circuit and/or the test generation process. Procedures to identify undetectable faults and remove redundant faults were described in [9]-[11]. The definitions from [12] and [13] are used in these procedures. Selection of partial scan flip-flops: The partial scan selection procedure of [14] achieves the same fault coverage as full scan design by eliminating sequentially undetectable faults. The efficiency of the procedure is due to the use of several scan selection phases based on difficult to control flip-flops, and fast identification of undetectable faults. Sequential ATPG is invoked only in the last phase, when several flip-flops are already scanned, and the circuit is easier to handle by ATPG. The tools can currently handle single clock designs consisting of basic gates and D flip-flops. We are extending the tools to handle multiple clock designs and other primitives.