Test generation for I/sub DDQ/ testing of bridging faults in CMOS circuits

Abstract

This paper describes a test generation methodology that supports test generation for bridging faults in CMOS circuits using I/sub DDQ/ testing or quiescent supply current observation. A modular, hierarchical approach is used to handle large circuit sizes while maintaining an accurate representation of the structure of CMOS designs and fault mechanisms. The emphasis of this work is on the efficient generation of I/sub DDQ/ test sets that achieve very high fault coverage of unrestricted bridging faults, including both gate- and switch-level bridging faults, with reasonable computational requirements. An implementation of the approach supports all operations required for automatic test pattern generation, including fault sensitization, fault simulation, and test set compaction. Results are presented for tests of realistic bridging faults derived directly from the CMOS layouts of a set of benchmark circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>