Abstract
In modern SoCs, process variations represented as process corners, which designers deal with sufficient design margins. As feature sizes shrink below 90 nm, the effects of process variations are also increasing severely. Moreover, circuit performance and power consumption are strongly impacted by environmental conditions under which the circuit operates. For example, thermal hot spots increase leakage, degrade timing/stability, and reduce battery lifetime. Both of increasing process variations and environment variations are now modeled in design corners, and corresponding design margin overheads have reduced the benefit of shrinking process node. In this paper, we first address the design margin problem. With accurate temperature sensor and speed sensor implemented in our SoC application, we can measure the process and environment variations on each chip. Proceeding on-filed design model correlation with realistic variation information can further reduce unnecessary design margins and improve the accuracy of process modeling. Furthermore, we can utilize the temperature sensor to construct the temperature profile, and improve the system performance and power consumption.
Published Version
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