Test environment for verification of multi-processor memory subsystem unit

D.a Lebedev ,M.v Petrochenkov

doi:10.15514/ispras-2019-31(3)-6

Abstract

State of the art microprocessor systems usually include complex hierarchy of a cache memory. Coherence protocols are used to maintain memory consistency. An implementation of memory subsystem in HDL (hardware description language) is complex and error-prone task. Ensuring the correct functioning of the memory subsystem is one of the cornerstones of a modern microprocessor systems development. Functional verification is used for this purpose. In this paper, we present some approaches for verification of memory subsystem units of multi-core microprocessors. We describe characteristics of memory subsystems that need to be taken into account in the process of verification. General structure of test environment for stand-alone verification of memory subsystem units is presented. Classification of checking model types and their advantages and disadvantages are described. The approach of construction of a standalone verification environment using Universal Verification Methodology (UVM) is presented in the paper. Restrictions that should be taken into account when verifying memory subsystem unit are listed. The generation stimulus algorithm stages are presented. Method of using “hints” from design under verification to eliminate nondeterminism is used in the implementation of checking module. We review several other techniques for checking the correctness of memory subsystem units, which can be useful at different stages of project development. A case study of applying the suggested approaches for verification of Home Memory Unit of microprocessors with Elbrus architecture is presented. Classification of detected and corrected errors in different submodules of verified device is provided. Further plan of the test system enhancement is presented.

Highlights

With the development of microprocessor technology and growth of the number of computational cores and CPUs in systems processor performance increases rapidly
Additional function of the assertions, which was used in the test system, is detection of the discrepancy between coherence protocol specification and generated requests types in the certain cache lines states
The disadvantage of this approach is the limitation of the properties of the verified device that can be checked by assertions

Summary

Introduction

With the development of microprocessor technology and growth of the number of computational cores and CPUs in systems processor performance increases rapidly. To level the difference in speed, designers of microprocessor systems implement a complex memory subsystem that includes cache hierarchy. State of the art microprocessor systems usually include 3-4 levels of cache memory. This approach is able to reduce the number of accesses to main memory, and, reduce memory access instructions average execution time. A memory subsystem and implementation of coherence protocols in HDL (Hardware Description Languages) models must be thoroughly verified [2]. It is essential to mention that some of the components of a memory subsystem are invisible from the point of view of a testing program and it is hard to recreate necessary conditions for verification with proper quality. There are a number of methods to implement a standalone functional verification of a memory subsystem.

Standalone verification methods of memory subsystem

Using gray box approach for verification of home memory unit

Results