Test device structures for integrated circuit design, process technology development and evaluation

Abstract

In the present paper, mask contours of npn transistors, pnp lateral transistors, diffused and pinch resistors, bridge and Greek cross sheet resistors, metal to doped silicon region contact resistors, parasitic pnp transistors, test diodes and alignment marks have been drawn (500 ×) for the development and testing of integrated circuit design and technology. The layout design of devices is based on 10 μm design rules with defined minimum dimensions and clearances in order to avoid the failure of the circuit due to technological inaccuracies. Devices could be easily designed, fabricated and performance evaluated in a fairly good R & D set-up having semiconductor device fabrication facilities.