Abstract
Integrated circuit (IC) applications have become viable, reliable, and cheaper with deep-submicron technologies in VLSI industry. SoC (system on chip) is a microchip, which holds the necessary hardware and software to implement various functions onto a single chip. An IC should be tested during design process to check the correctness of the design and also to check the functionality of the design after fabrication. Testing cost shares almost half of the manufacturing expenditure. Achieving high-test quality in reduced VLSI geometry increases the complexity of the testing methods because of huge volume of test data. Automatic testing equipment (ATE) reduces testing efforts, but it has limited memory in comparison with the huge volume of the test data. One of the methods to reduce the burden of ATE is test data compression. The advantages of test data compression are as follows: (i) reduction in memory requirement for ATE and (ii) reduction in testing time. Though many advanced algorithms are used for testing of VLSI circuits, most of them are expensive in terms of test data volume and power. This survey discusses all the test data compression methods, and it helps the researchers in testing domain.
Published Version
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