Test chip for inductance characterization and modeling for sub-100nm X architecture and Manhattan chip design

Abstract

This paper deals with the measurement and modeling of on-chip interconnect inductance in a VLSI chip fabricated using a sub-100 nm copper (Cu) CMOS process. A test chip was designed and fabricated in a 90 nm process node, to study the inductive effects, with various inductive return paths, including substrate, co-planar structures, power grids, and random structures. S parameter measurements were made on these structures to extract wire inductance and skin effect. It was observed that the presence of CMP dummy metal fills influences the inductive behavior and skin effect of the Cu process. Inductive effects for Cu interconnects are then compared with previous studies on aluminum (Al) interconnect at 130 nm. This is followed by a discussion on the significance of inductance effects in sub-100 nm X architecture chip design.